Intel Blog Post: The More the Merrier – Integration and Virtual Platforrms

Integration is hard, that is well-known. For computer chip and system-on-chip design, integration has to be done pre-silicon in order to find integration issues early so that designs can be updated without expensive silicon re-spins. Such integration involves a lot of pieces and many cross-connections, and in order to do integration pre-silicon, we need a virtual platform.

But that virtual platform needs to be built as well – and it is its own integration project, pulling in a wide variety of models from as wide variety of sources, and written using any number of virtual platform frameworks.

In a blog post at the Intel Developer Zone, I go through a bit more of what it takes to build an integrated virtual platform to support platform integration work, and how that integrated virtual platform can be integrated into system-level continuous integration workflows.

Was that a sufficient number of “integrations” in a sentence?

The contents of the blog post reflect the materials that I had prepared for a talk at the 54th Design Automation Conference (DAC), but that I unfortunately could not present myself (for a list of my talks, see http://www.engbloms.se/jakob_presentations.html).

Final Note

Note: this blog post comes a few weeks after the post on the Intel blog. That post came out while I was on vacation, and then I never got around to writing about it on this blog.

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