A comment-on-comment:

deriving all the models and deliverables for a piece of IP – from fast functional VP kinds of simulation models through to the actual RTL implementation plus testbenches – through an automated configuration and generation process (as we do at Tensilica).

I think that is an excellent point, but that achieving this in practice for general hardware seems hardware than when using a more focused tool such as the Tensilica system. Being “restricted” to that particular class of problem should make this much simpler than when applying it to arbitrary hardware.

Also, the second problem which the panel did not address (as this was about new chip design mainly due to the context in a chip design conference) is how to model all the stuff that is already out there… most of a new system is old hardware that already exists, and that also needs to be modeled to get a complete system to run software on. And there, good old manual programming of device models is hard to get around.