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Observations from Uppsala Computer Simulation, Virtual Platforms, Embedded Programming, Multicore and More (by Jakob Engblom)

Tag Archives: Amd

Coding Horror on Big Iron Hardware

2009 July 15 20:41 / Leave a Comment / Jakob

opinionIn a post from late June, Jeff Atwood at Coding Horror discusses the horrible cost of a large HP server (scaling up to 32 processor cores in eight AMD x86 sockets), compared to a bunch of simple single-socket basic servers. There are some interesting notes on relative costs of small-and-simple servers, including things like administration and power. There is an undercurrent to the post and the comments that the big HP machine is “overpriced”. I don’t think it is. If you have ever had Erik Hagersten as a teacher in computer architecture, you will know why.

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Posted in: multicore computer architecture / Tagged: AMD, CodingHorror, HP, Jeff Atwood, server

Three Cores make a Crowd — or a Problem

2009 February 7 22:12 / 2 Comments / Jakob

mpc8640d_ppA common question from simulation users to us simulation providers is “can I simulate a machine with N cores”, where N is “large”. As if running lots of cores was a simulation system or even a hardware problem. In almost all cases, the problem is with software. Creating an arbitrary configuration in a virtual platform is easy. Creating a software stack for that arbitrary platform is a lot harder, since an SMP software stack needs to understand about the cores and how they communicate.

Essentially, what you need is a hardware design that has addressing room for lots of cores, and a software stack that is capable of using lots of cores — even if such configurations do not exist in hardware. Unfortunately, since software is normally written to run on real existing machines, there tends to be unexpected limitations even where scalability should be feasible “in principle”.

Here is the story of how I convinced Linux to handle more than two cores in a virtual MPC8641D machine.

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Posted in: multicore computer architecture, multicore software, virtual platforms / Tagged: AMD, device tree, freescale, linux, Linux kernel, mpc8641d, OpenPIC, Simics

Is Cycle Accuracy a bad Idea?

2008 July 11 22:45 / 8 Comments / Jakob

In a funny coincidence, I published an article at SCDSource.com about the need for cycle-accurate models for virtual platforms on the same day that ARM announced that they were selling their cycle-accurate simulators and associated tool chain to Carbon Technology. That makes one wonder where cycle-accuracy is going, or whether it is a valid idea at all… is ARM right or am I right, or are we both right since we are talking about different things?

Let’s look at this in more detail.

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Posted in: computer simulation technology, EDA, ESL, virtual platforms / Tagged: AMD, ARM, Axys, Carbon Technology, clock-cycle models, CoWare, cycle accuracy, DEC, Grant Martin, IBM, Infineon, Intel, Modeling, rtl, scdsource

More Odd Targets

2008 March 27 16:21 / Leave a Comment / Jakob

Intel Core 2 QuadPC Perspective writes in its IDF writeup about Intel’s upcoming Dunnington device with six cores on a die. Another break from the 2-4-8 powers-of-two progression. Feels oddly refreshing, even if it is really nothing very strange about it. Just like AMDs triple-core.

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Posted in: multicore computer architecture / Tagged: AMD, Intel, odd core count

AMD three-core Phenom

2007 September 19 20:00 / 1 Comment / Jakob

Spotted at EETimes.com – Odd move: AMD plans three-core CPU . Interesting that someone in the mainstream finally breaks the 1-2-4-8 progression that seems to be the norm.

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Posted in: multicore computer architecture / Tagged: AMD, EETimes, odd core count, Phenom, Xenon

SICS Multicore Day August 31

2007 September 2 21:13 / 10 Comments / Jakob

The SICS Multicore Day August 31 was a really great event! We had some fantastic speakers presenting the latest industry research view on multicores and how to program them. Marc Tremblay did the first presentation in Europe of Sun’s upcoming Rock processor. Tim Mattson from Intel tried hard to provoke the crowd, and Vijay Saraswat of IBM presented their X10 language. Erik Hagersten from Uppsala University provided a short scene-setting talk about how multicore is becoming the norm.

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Posted in: appearances, conferences, embedded software, embedded systeme, multicore computer architecture, multicore debug, multicore software, parallel computing, uncategorized / Tagged: AMD, Erlang, Hardware debug support, IBM, Intel, Joe Armstrong, Niagara, QuviQ, SiCS Multicore days, Sun, transactional memory, UltraSPARC

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