DVCon Europe 2018 / A Few Cool Papers

DVCon Europe took place in München, Bayern, Germany, on October 24 and 25, 2018. Here are some notes from the conference, including both general observations and some details on a few papers that were really quite interesting. This is not intended as an exhaustive replay, just my personal notes on what I found interesting.

Continue reading “DVCon Europe 2018 / A Few Cool Papers”

Talking about Temporal Decoupling at DVCon Europe

This year’s Design and Verification Conference and Exhibition (DVCon Europe) takes place on October 24 and 25 (2018).  DVCon Europe has turned into the  best conference for virtual platform topics, and this year is no exception. There are some good talks coming!

Continue reading “Talking about Temporal Decoupling at DVCon Europe”

Presenting about Simics and SystemC at DVCon Europe 2016

I am going to present a paper about our new SystemC Library in Simics, at the DVCon Europe conference taking place in München next month. The paper is titled “Integrating Different Types of Models into a Complete Virtual System – The Simics SystemC* Library”, and I authored it together with my Intel colleagues Andreas Hedström, Xiuliang Wang, and Håkan Zeffer.

Continue reading “Presenting about Simics and SystemC at DVCon Europe 2016”