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Observations from Uppsala Computer Simulation, Virtual Platforms, Embedded Programming, Multicore and More (by Jakob Engblom)

Tag Archives: Intel

Does ISA Matter for Performance?

2012 December 23 22:54 / 6 Comments / Jakob

When I grew up with computers, the big RISC vs CISC debate was raging. At the time, in the late 1980s, it did indeed seem that RISC was inherently superior to CISC. SPARCs, MIPS, and Alpha all outpaced boring old x86, VAX and 68000 processors. This turned out to be a historical parenthesis, as the Pentium Pro from Intel showed how RISC-style performance could be mated to a CISC ISA. However, maybe ISAs still do matter.

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Posted in: computer architecture / Tagged: 32-bit, 64-bit, 68000, ARM, CISC, instruction set architecture, Intel, ISA, MIPS, performance optimization, power architecture, RISC, SPARC, x86

Wind River Blog: Crystal Forest on Simics

2012 March 12 12:08 / Leave a Comment / Jakob

There is a new post at my Wind River blog, about Simics running a model of the new Intel Crystal Forest platform. Crystal Forest is a very complex piece of hardware, but I am pretty happy that we managed to demo it in an understandable way – by essentially using it as a black box and putting a pretty display on top of that (using Eclipse).

 

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Posted in: virtual platforms, Wind River Blog / Tagged: Crystal Forest, Intel, Simics

S4D 2010

2010 September 15 09:02 / 12 Comments / Jakob

Looks like S4D (and the co-located FDL) is becoming my most regular conference. S4D is a very interactive event. With some 20 to 30 people in the room, many of them also presenting papers at the conference, it turns into a workshop at its best. There were plenty of discussion going on during sessions and the breaks, and I think we all got new insights and ideas.

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Posted in: appearances, computer simulation technology, conferences, EDA, multicore debug, security, virtual platforms / Tagged: ARM, Debug, ESCUG, FDL, Infineon, Intel, John Aynsley, Pat Brouillette, S4D, Simon Davidmann, Southampton, ST, SystemC, Thorsten Grötker, TrustZone

Is Cycle Accuracy a bad Idea?

2008 July 11 22:45 / 8 Comments / Jakob

In a funny coincidence, I published an article at SCDSource.com about the need for cycle-accurate models for virtual platforms on the same day that ARM announced that they were selling their cycle-accurate simulators and associated tool chain to Carbon Technology. That makes one wonder where cycle-accuracy is going, or whether it is a valid idea at all… is ARM right or am I right, or are we both right since we are talking about different things?

Let’s look at this in more detail.

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Posted in: computer simulation technology, EDA, ESL, virtual platforms / Tagged: AMD, ARM, Axys, Carbon Technology, clock-cycle models, CoWare, cycle accuracy, DEC, Grant Martin, IBM, Infineon, Intel, Modeling, rtl, scdsource

David Ditzel Interview at The Register/Semicoherent Computing

2008 May 9 18:10 / Leave a Comment / Jakob

TheRegister Radio LogoThe Register has a few podcasts in addition to their website, and the one called “Semicoherent Computing” has turned into a very nice series of interviews with interesting people from the computer industry. I recently listened to their interview from September 2007 with David Ditzel of Transmeta fame. He had a lot to say about the history of computing, as well as interesting things on where computing is going. Well worth a listen! Particular interesting highlights…

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Posted in: computer architecture, multicore computer architecture, virtual machines / Tagged: heterogeneous, homogeneous, IBM, Intel, Niagara, power architecture, Rock, Sun, Transmeta

More Odd Targets

2008 March 27 16:21 / Leave a Comment / Jakob

Intel Core 2 QuadPC Perspective writes in its IDF writeup about Intel’s upcoming Dunnington device with six cores on a die. Another break from the 2-4-8 powers-of-two progression. Feels oddly refreshing, even if it is really nothing very strange about it. Just like AMDs triple-core.

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Posted in: multicore computer architecture / Tagged: AMD, Intel, odd core count

Dekker’s Algorithm Does not Work, as Expected

2008 January 7 22:14 / 15 Comments / Jakob

Sometimes it is very reassuring that certain things do not work when tested in practice, especially when you have been telling people that for a long time. In my talks about Debugging Multicore Systems at the Embedded Systems Conference Silicon Valley in 2006 and 2007, I had a fairly long discussion about relaxed or weak memory consistency models and their effect on parallel software when run on a truly concurrent machine. I used Dekker’s Algorithm as an example of code that works just fine on a single-processor machine with a multitasking operating system, but that fails to work on a dual-processor machine. Over Christmas, I finally did a practical test of just how easy it was to make it fail in reality. Which turned out to showcase some interesting properties of various types and brands of hardware and software.

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Posted in: multicore computer architecture, multicore software, programming / Tagged: code example, Dekker's Algorithm, Embedded Systems Conference, freescale, Intel, mpc8641d, race condition

Book Review: Intel’s Multicore Programming Book

2007 December 9 21:43 / 2 Comments / Jakob

Multicore programming book coverThe book “Multicore Programming – Increasing Performance through Software Multithreading” by Shameem Akhter and Jason Roberts is part of a series of books put out by Intel in their multicore software push. In case you have not noticed, Intel has a huge market push currently where they give seminars, publish articles and books, and give curricula to universities in order to get more parallel software in place. I read this book recently, and here is a short review.
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Posted in: multicore computer architecture, multicore software, programming, review / Tagged: books, Intel, Itanium, Jason Roberts, Multicore programming, OpenMP, Shamemm Akhter, SMT

Intel ARK

2007 November 15 20:28 / Leave a Comment / Jakob

Intel has a really neat tool on their homepage: the Intel ARK — Automated Relational Knowledgebase.  It is a horrible name for a brilliant tool: it lets you search for processor names, codenames, chipsets, and jump around in a database of processor variants, compatible chipsets, feature lists, and more. Not that I care particularly about Intel chips, but the tool is something everyone selling silicon devices should copy. Being able to quickly figure out just what is inside a certain device (and what is not), and finding related devices and compatible chips is just brilliant for curious people, customers, and supporting services.

Please, everybody else?

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Posted in: computer architecture / Tagged: ARK, Intel

SICS Multicore Day August 31

2007 September 2 21:13 / 10 Comments / Jakob

The SICS Multicore Day August 31 was a really great event! We had some fantastic speakers presenting the latest industry research view on multicores and how to program them. Marc Tremblay did the first presentation in Europe of Sun’s upcoming Rock processor. Tim Mattson from Intel tried hard to provoke the crowd, and Vijay Saraswat of IBM presented their X10 language. Erik Hagersten from Uppsala University provided a short scene-setting talk about how multicore is becoming the norm.

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Posted in: appearances, conferences, embedded software, embedded systeme, multicore computer architecture, multicore debug, multicore software, parallel computing, uncategorized / Tagged: AMD, Erlang, Hardware debug support, IBM, Intel, Joe Armstrong, Niagara, QuviQ, SiCS Multicore days, Sun, transactional memory, UltraSPARC

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