The z10 is the latest generation of the classic IBM mainframe family that started with S/360 back in the 1960s. The simulation for just running the firmware of these beasts is making most other virtual platforms look positively puny – focusing on single SoCs for consumer or digital devices. It also shows that virtual platforms as a technology can scale all the way from single-core bare-metal simple machines that are useful for developing initial software for simple embedded systems up to servers and racks containing hundreds of processing units and very diverse hardware.

The teminology used is unusual, compared to the EDA/ESL and computer architecture research worlds. But it is good. The key concept is a “VPO”, Virtual Power On. For a computer of this class, doing Power On is a major event, and calling it a “boot” does not really cover its full complexity, involving many different layers of software running on the same and different computers. The VPO was targeted at four months prior to hardware tape-out — and this means that at that point in time the virtual system would be complete and the firmware complete enough to do a power on.

The simulation system used for the z10 mixes IBM’s in-house CECsim with Virtutech Simics. CECsim executes the code for the central zSeries processors, while Simics simulates the FSP-1 “flexible support processor” based on the Power Architecture. In previous generations of simulation, the FSP code had been host-compiled and run on an x86 workstation instead of running the actual Power Architecture binaries. Running the real binaries brought additional verification value to the software, finding 3 times more bugs than in the previous host-based simulation:

Because the Simics environment now enables us to execute all FSP code in simulation, a far greater amount of code is simulated. Correspondingly, the number of defects found in simulation also increased, by more than 33(Table 2).

The article also describes how hardware-accelerated simulation of the actual VHDL of complex new IO chips were used to validate the bits-and-cycles-level interfacing between code and the logic, as well as to validate the logic design itself.

Overall, the article is one of best presentations of comprehensive use of various types of simulation tools and techniques to remove firmware defects as early as possible in the system development project.

For more on the history of this, I refer to a previous blog post here, “The 1970 rules strikes again“, where I described some late 1960′s mainframe simulation technology and its uses. Also, browse the back issues of the IBM JRD archives, there are lots of nuggets to be found there!

Seems like the next step after that has a processor called “z6″, and the slide below, taken from a nice presentation available on-line from IBM, appears to indicate that the actual machines will also be called “z6″. Wikipedia has a different opinion, stating that the next-gen mainframes will appear on 2008 Feb 26, and be called z10. Update: the machines are called z10, while the CPU is called z6. Quite logical. But I leave my mis-speculation in here for the record anyway.

Interestingly, that is just two days from now, so we will soon find out. I am posting this post anyway now, since the name is the least interesting

The new processor powering it has some interesting properties, including on-chip accelerators for various functions.

First of all, it seems to be a quite close relative to the Power6 processor. It also aims for very high clocks and the CPU architecture (slide 7) also mentions grouping of instruction and other ideas that are similar to the Power4/5/6 lineage of chips. The “z6″/”power6″ common number “6″ is likely an accident, since IBM has been counting up to that level with the CMOS integrated mainframe processors independently of the Power Architecture development.

The z6 has four cores on a single die rather than the two cores by two threads employed in the Power 5/6. Probably, the different types of applications and ISAs targeted makes threading less

What is the most interesting though is the return of the co-processor, or as they are called nowadays, accelerators. This beast has a decimal floating point unit shared with the Power6 design (one unit inside each core). Similar to Sun’s Niagara 2, there is also compression and cryptography acceleration on the processor chip (one unit shared by two cores). It is not the kind of massive acceleration employed in recent embedded processors, but it is (yet) another sign that heterogeneous computing is becoming fashionable.

From a historical perspective, dedicated accelerators for various specific functions in order to offload the main processors was one of the initial reasons that mainframes could handle the high loads that they did. The “channel controllers” that designed in even back in the 1960s have always been key to the fantastic scaling and robustness of the mainframes. Had they been introduced today, they would have been called “IO accelerators” or “IO offload engines”. In principle, the IBM channel controllers are the grandfathers of today’s TCP/IP accelerators, smart Ethernet controllers, Fibre Channel controllers, and their ilk. So having on-chip acceleration for certain functions that can benefit from high bandwidth memory access and a short communication path to the processor is a very natural evolution for the mainframe architects.