The book “Taxonomies for the Development and Verification of Digital Systems“, edited by Brian Bailey, Grant Martin, and Thomas Andersson, was published in 2005 by Springer Verlag. It is a legacy of the defunct VSIA, and presents an attempt to bring order to nomenclature and taxonomies in the chip design field (its scope is defined to be broader than that, but in essence, the book is about SoC design for the most part).
The book is obviously a collection of previous work, and the style is quite inconsistent from section to section. Not so much that it detracts from the value of the information, but it does feel a bit rushed.
The book presents four sets of taxonomies:
- Models, which is by far the richest part. In addition to a definition of terms in the field of building models of digital systems, it also offers a detailed classification scheme for the models. The classification scheme uses five “resolution” axes along with an external/internal perspective to define what a model contains and at what level of resolution.
- Functional Verification, which is really just a collection of terms.
- Platform-Based Design, which is more of a marketing discussion in how to define and design platforms. Also mostly a definition of terms.
- Hardware-Dependent Software (HdS), which defines terms. It has some attempts to classify software along some axes, but it does not really work out too well.
The main value is really in the second chapter, where it does provide a decent basis for discussing the level of abstraction at which models are created (note that accuracy is different from abstraction: a very detailed model at a very low level of abstraction can be totally off when considered from an accuracy perspective).
However, I fear that the impact of this work has been fairly limited. No discussion on modeling that I have been participating in has really gone back to this basis and worked from there. I think a key problem here is that the material is only available as a quite expensive book from Springer, rather than as a freely downloadable document on the web. It is clear to me that spreading ideas today depends on free and easy digital access to the information… that’s why I have my own publications page up to make stuff that I have created available for reading.
The hardware-dependent software (HdS) section gave rise to several “but they forgot X” comments from my part. For example, it is missing important aspects like processor virtualization, hypervisors, and IO virtualization (which totally change the game on HdS). Also, SMP operating systems are only giving a passing reference, with the focus on uniprocessors. And why do people keep using the term “Rate-Monotonic Analysis? There are so many much more modern fixed-priority scheduling analysis theories, methods, and tools available that RMA is like talking about programming in assembler…
What a choice for summer vacation reading… and thanks to Bart Vanhournout at CoWare for the tip about the book in a discussion trying to pin down abstraction levels.
Jakob
Thanks for the review. Some background might help with the concept of the book. It was conceived in the summer of 2004 at a point in time where VSIA and all the work that it had done seemed as though it might go away forever, and the model taxonomy, one of the most downloaded documents produced by VSIA members, might disappear. The idea was to put some of this work quickly into document form so that they would continue to be available to people if VSIA did go away. Somewhat ironically, the VSIA web site and documents still seem to be accessible so perhaps this was not really necessary – and it did end up as a relatively expensive book. This also explains why some of the virtualisation terms are missing – these were not active concepts when the work was being done (as long as a decade ago) and no doubt many of these areas could stand a significant update to reflect today’s concerns, which also go beyond SoC design (which was the VSIA focus).
I’m not sure by your final comment whether you enjoyed reading it in the summer or found it a bit painful! But thanks for the review.
Grant Martin
Let me add to what Grant said. The VSIA model taxonomy was itself an extension of work done on the DARPA RASP program and thus does represent an enormous effort over a space of 10 years or more. We have also not let the work languish, and in our latest book “ESL Design and Verification: A prescription for electronic system level methodology”, we extended the model taxonomy into the ESL space, something that people in the industry have said is worth the price of the book alone.
Thanks for background, that is exactly what I did not quite get from the book itself. Is the updated taxonomy available for download, or just in the book?
Also, are the diagrams in the model taxonomy available somewhere where the difference between dark grey and light grey is really clear? That part was a tad hard to read…
The ESL taxonomy is just in the ESL Design and Verification book. As Brian said, since some people have commented that it is worth the price of the book we encourage people to buy it! (and it is much more economical than a Springer book as Elsevier tends to price many of their books lower). If the Springer book gets revised sometime, your point about improving the diagrams is a good one.
Thanks for taking the time to review the book. In addition to the points made by my co-editors, I want to note that we did not just slap the VSIA taxonomies together and add a cover. We cleaned up the grammar and formatting, updated several sections based upon latest industry practices, and fixed a bunch of inconsistencies between the original VSIA documents. So I think that the result was worth the effort, although the book has had limited impact. Your review should help!