Carbon Design Systems keeps putting out interesting blog posts at a good pace. 
Bill Neifert at recently put up a blog post about the various of speed/accuracy tradeoffs you can make when building virtual platforms. The main message of the blog is that you should use a mix of fast models (TLM + JIT, like the ARM Fast Models) and cycle-accurate generated-from-RTL models (like the models generated by Carbon’s tools). By switching between the levels of abstraction when you need to go fast or go deep, you get something that is pretty much the best of both worlds (I already blogged about the change between abstraction before). It makes perfect sense, and I am all with him. There are dragons in the middle land.
However, I do not quite agree with Bill about the absolute uselessness of the intermediate types of models, like SystemC TLM-2.0 AT. Basically, what is traditionally called “cycle accurate modeling” (while not derived from RTL).
I love the illustration on their blog post:
But that land of dragons sometimes have to be visited, for those daring knights of design that need to peek into the future.
If the goal is to build a model that describes a piece of hardware at cycle accuracy, manually coded AT models are the wrong way to go (see this blog post about the futility of cycle accurate model building). You will never be quite right, and the resulting model won’t be that much faster than a model derived from RTL.
However, if we look at the case of designing new hardware, the dragon area is the right place to be. Before you have RTL, you cannot be cycle-accurate to the final implementation, since that does not yet exist. Rather, you want a model that lets you try various latencies and pipelines and parallelization strategies and estimate the eventual performance. This has been the standard way to develop new processors since the late 1950s, and still is. James Aldis of TI had a nice description of the process in an article from last year.
The key take-away for me is that anyone who does not either have access to the RTL of a processor or a direct connection to the design team pretty much have to give up on hoping for “cycle accurate” models. In any case, once we start moving away from the processor, out into peripherals and then off-chip, we soon run out of precise models no matter what. A virtual platform can be perfectly useful for most use cases, even when it is only a fast platform with no attempt at cycle accuracy.
How about simulating your design with plain old FPGA?
Or just build a tweak-able prototype or a very small test batch.
I can write assembly code on bathroom tissue and it will not mean a thing until executed by a machine and yet the correctness is there. The machine could see the code OCR it to a text file, compile it and execute it.
You my friend are an imbecile. you are the typical idiot computer guy.
Seems like Bowerick Wowbagger visited.
Nice try. You are so retarded that you are beyond repair. You are just spitting some stupid senseless English constructs. Do you get paid by word count? I guess the word imbecile was created to describe you.