The instruction set simulator (ISS) is a core component of any virtual platform. The instruction set that the ISS simulates determines which software will work (and not work) on a virtual platform (VP) containing it. Most of the VP execution time tends to be spent in the ISS, even though the number of ISS objects in the VP is typically much smaller than the number of peripheral device models. In most cases, the performance of the ISS is critical to the overall performance of the virtual platform.
The Intel® Simics® simulator features a very high-performance instruction-set simulator framework that has been used to simulate more than two hundred different processor core variants from a dozen or so instruction-set families. To achieve its speed, the instruction set simulators in the Intel Simics simulator use a mix of a classic interpreter, a just-in-time (JIT) compiler, and virtualization.
The ISS for a particular processor core can use all three execution modes within a single simulation run. The strategy is to always use the fastest mode possible for the current target code, falling back to slower modes when necessary. A single simulation run will most likely feature a mix of execution modes over time – it is not typically the case that everything is run in just a single mode.
Compared to other VP frameworks, what is pretty unique about this setup is the combination of high performance simulation with precise timing and the use of multiple modes of execution at once. Most of the time, you get one of these.
