EETimes.com – Multicore CPUs face slow road in comms

eetimes logoThe  EETimes article Multicore CPUs face slow road in comms piqued my interest. There is an interesting chart in there about just how slow more-than-one-core processors will be in penetrating a vaguely defined “comms” market place. I can believe that, but I think their comments on the PowerQUICC series require some commentary…

Essentially, the article is a report on a talk by Linley Gwennap at the Multicore Expo last week. The most interesting point are that simple single-core processors are taking over from the traditional heterogeneous processor + big accelerator pattern examplified by the Freescale PowerQUICC series. And that even Freescale themselves are “replacing” PowerQUICC chips based on the venerable CPM with “simpler dual-core chips”, which has to mean the MPC8572 currently and probably the QorIQ P2000-series chips later on.

The main point is that people are moving away from the “complexities” of the CPM-style heterogeneous hardware design, to symmetric multiprocessing designs that are simpler in one way. But harder to program when you want to have a regular old program use more than one core, as we all well know. It is a good question whether this is actually the case: I am not too sure that correctly writing a parallel threaded program for a shared-memory multiprocessor is easier than calling a hardware accelerator API or using a heterogeneous architecture… more familiar to general-purpose programmers, sure. But easier? Not necessarily.

What I do take some issue with is the implication that the quad-core and dual-core processors expanding into the market, in Gwennaps opinion, do not have these “complex hardware accelerator APIs”… all the hardware I have seen for the comms field certain feature very powerful offload and acceleration engines for tasks like network interface, TCP/IP processing, regular expression matching, security computations, etc.

Look at the feature sets of chips like the Freescale QorIQ P4080 or the Cavium Octeon Plus CN58xx family: their core acceleration engines look every bit as complex as the old CPM to me. The programming might be a bit different, their presence spun as accelerators rather than as a processor in the marketing talk, but still they are complex acceleration blocks that definitely have a lot of power. They also seem quite intent on staying and proliferating, and not going away. I see no sign that the future of computing is anything but lots of programmable cores augmented by lots of accelerators. The benefits of heterogeneous architectures in terms of power, throughput, and chip size are simply too compelling.

What is interesting in the article is also both the claimed poor state of software that is slowing the adoption of multicore, and that this means that the software stacks actually get some more time than could be expected to adapt to multicore and truly parallel hardware.

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