About two months ago, Cavium Networks launched their second generation of Octeon chips, the Octeon II. The most obvious difference to the previous generation (Octeon, Octeon Plus) is a new MIPS64 core with much better support for hypervisors and virtualization. There are some other interesting aspects to this chip, though.
First, they launch with 2 to 6 cores in typical chips, far short of the 32 core maximum. That probably indicates that system builders have a hard time adopting and getting good use from manycore architectures currently.
It is also a system that is full of accelerator units! In a 6-core chip, you find some 75 accelerator units according to Cavium. That is ten times as many accelerators as main cores, indicating where a large part of the work is actually being performed. To me, this validates that heterogeneous architectures and accelerators are still useful and valuable for networking applications, and that the idea of a homogeneous sea of identical processor cores with no specialization and no fixed-function hardware accelerators is still distant (I think it will never happen, but you never know).