The S4D Debug Conference

S4DAn unplanned and unexpected bonus with my trip to the FDL 2009 conference was the co-located S4D conference. S4D means System, Software, SoC and Silicon Debug, and is a conference that has grown out of some recent workshops on the topic of debugging, as seen from the perspective of hardware designers (mostly). S4D was part of the same package as FDL and DASIP, entrance to one conference got you into the other two too. As I did not know about S4D until quite late in the process, this was a great opportunity for me to look at what they were doing.

It was sufficiently interesting that I spent all of Thursday in S4D rather than in  FDL. It was really the first time that I have seen so many people working with practical embedded systems debug in the same room. Debug tends to be a topic at embedded systems conferences of various kinds, but then mostly from a fairly superficial technical perspective: assuming fairly simple software tools. Here,  there were presentations on how current hardware debug is being extended to incorporate powerful trace and debug and synchronous stop facilities.

It was very interesting to see Infineon, ST, and ARM present their work in on-chip debug. Users at ST, Nokia and Continental presented their view of debug requirements, uses, and current home-grown tools. There were presentations from EDA vendors showing off debuggers for hardware designs and some virtual platforms tools for software debug. Freescale presented how their HyperTRK debug agent works with their P4080 hypervisor, covering the software-instrumentation approach. Debug tends to be a field neglected by academia, but there were some academic papers presented as well. gdb7‘s multi-threaded debug abilities were mentioned. Pretty much the only topic missing in action was reverse execution.

This mixed audience gave rise to quite a few interesting discussions during the day. It was simple fun, as far as I am concerned.

The following were the main themes addressed and discussed:

  • How to make customers of silicon chips appreciate the on-chip debug and not just consider it an unnecessary cost that could be avoided if only their software engineers did not make any mistakes. Answer: sell it as a performance optimization tool instead.
  • Multicore debug, including hardware-supported tracing and synchronized stop of multiple cores on a single SoC.
  • Given that we have massive traces from hardware and software debug and trace facilities, how can we actually find errors? Processing of trace information to detect anomalies is going to be an important issue in the future.
  • Performance bugs are the next frontier, after current concerns with functionality bugs.

If I were to take a critical look at the conference and its scope, there were some things that were not covered.

  • System-level debug, outside the scope of a single SoC, was not in any talk.
  • Almost all the speakers and attendees came from the world of consumer electronics and automotive systems. It would have been nice with some input from long-time parallel world of servers and operating systems, such as Microsoft’s debugger teams. In a sense, this is the inverse of my complaint about the SiCS Multicore Day 2009.
  • As well as compiler people involved in creating debug information and how they deal with parallel programs.
  • Security vs debuggability, a favorite topic of Joachim Strömbergsson. It would have been fun if Joachim would have been there. I asked Rolf Kühnis from Nokia about security in MIPI, and he said that it simply was not in scope for MIPI: each manufacturer deals with it in their own way.

3 thoughts on “The S4D Debug Conference”

  1. Hi!

    I just wanted to add a comment on your statemant that “system-level debug was not in any talk”. Unfortunately you seem to have missed my talk on the second day, where I presented our approach to coordinate debug and test activities of a multitude of nodes of a distributed system. The approach is based on precisely synchronized time-of-day clocks used to trigger debug and test action, operating with little hardware overhead in the CPU chips.

    I add a link to one of our project websites in case a reader is interested in some more information:

    Best regards,

    Roland Höller

  2. You are right. You did talk about greater-than-SoC debug. The main issue with the hardware-synchronized approach is that you need a system small enough in physical size that you can keep it synchronized. But in essence, you are chasing the right thing: debug across multiple SoC, using extended on-chip logic that lets you do synchronized commands across the entire set.

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