computer architecture – Observations from Uppsala

Hi Local AI, Draw Me …

I recently built a new desktop computer, featuring an Intel ARC 770 graphics card (just to be different). The card is supported by the Intel AI Playground, which is a software package that makes it dead easy to run AI/large language models (LLM) locally on my GPU. I was curious as to just what this could do, as compared to the big AI models that run on cloud servers.

“Processor Performance Insights and Optimization” – Computer and System Architecture Unraveled Event Four

Finally, the fourth CaSA, Computer and System Architecture Unraveled, meetup happened on November 6. It took far too long to get it organized, but we finally did it. The theme was about processor performance analysis and efficient processor implementation, offering two talks from very different perspectives. The location was almost the same as before, on the 19^th floor of the Kista Science Tower building. Once more thanks to the sponsorship from Vasakronan and Kista Science City.

More Ghostwrite Bugginess with RISCVuzz

In my previous blog about the Ghostwrite vulnerability in the Alibaba T-Head C910 RISC-V-based processor, I noted that the authors of the paper had found more than just that one bug. The additional bugs are worth their own write-up, as they offer some more examples of what looks to be poor testing.

Ghostwrite – Now This is Weird

In August, a strange security vulnerability dubbed “Ghostwrite” was making the rounds in the press. Basically, a vector store instruction on an Alibaba T-Head C910 RISC-V-based processor would just write to a physical address without doing a virtual-to-physical translation or checking any kind of access rights. That is just totally weird. Just how could that be implemented and slip through testing???

The Event at the End of Universe

This is a short story from the world of virtual platforms. It is about how hard – or easy – it is to model a simple and well-defined hardware behavior that turns out to mercilessly expose the limitations of simulation kernels.

Useful Instruction Set Computing

I tend to get into discussions about computer processor instruction-set architecture (ISA) design. ISA design is far from my day job, but it is an interesting topic where everyone working with computers at the machine level have opinions. Typically based on a mix of personal experience and fond memories of particular machines. This in turn leads to intricate and intriguing arguments. In this blog, I will talk about my take on the current state of instruction sets in industry and the age-old “complexity of instruction set” question.

Schloss Dagstuhl (and a Seminar and Cerebras)

A month ago, I participated in a seminar at Schloss Dagstuhl in Germany, about “Discrete Algorithms on Modern and Emerging Compute Infrastructure”. Not my usual cup of tea, but it was very interesting and insightful nevertheless. I have attended a Dagstuhl seminar once before, back in 2003.

“RISC-V in Practice” – Computer and System Architecture Unraveled Event Three

On Wednesday, March 13, we had our third CaSA, Computer and System Architecture Unraveled, meetup. Same place as the previous, the 25^th floor of the Kista Science Tower building, thanks to the kind sponsorship of Vasakronan and our collaboration with Kista Science City. The theme this time was “The RISC-V ISA in Practice”, with two speakers named Björn. Another great event!

“Packet Networks are not Socket Science” – Computer and System Architecture Unraveled Event Two

On Wednesday, November 22, we had our second CaSA, Computer and System Architecture Unraveled, meetup. Same place in Kista as the last time, the 25^th floor of the Kista Science Tower building, thanks to the kind sponsorship of Vasakronan and our collaboration with Kista Science City. This time, the theme was networking – but not at the socket level. Per Holmberg presented how his team used “micro sleep” for power management in line-rate network processing, and Hans Brandberg talked about the Precision Time Protocol. Another great event!

The first Computer and System Architecture Unraveled Event in Kista – Great Speakers, Great Fun!

On the evening of the last Wednesday in September, we had our first CaSA, Computer and System Architecture Unraveled, event. CaSA is a meetup in Kista (Sweden) for people interested in computer architecture, system architecture, and how software and hardware interact down towards the lower levels of the stack. The topic for the inaugural event was “Core Count Explosion: A Challenge for Hardware and Software”, and it was great in some many ways!

Intel Blog: Playing with Instruction Sets in the Public Simics RISC-V Platform

As noted previously, the Public Release of the Intel Simics Simulator has added a simple RISC-V virtual platform.

In my second blog post about the platform, I reconfigure the instruction set, crash Linux, debug the issue, and reconfigure the software to match the hardware.

The NUC12 Enthusiast

Right when our old NUC5 died, its replacement had been delivered and brought online – a new Intel NUC12 Enthusiast, also known as the NUC12SNKi72 (I work at Intel, but even I find that name a bit obtuse). This is a seriously fast machine in a fairly compact package, even though admittedly not as small as the old NUC5. On the other hand, as a machine with an ambition to be a replacement for a dedicated gaming PC, it sports a dedicated graphics card and not just the integrated graphics typical for the classic NUCs.

SystemC Evolution Fika: Parallel SystemC

The SystemC Evolution Fika on April 7 had threading/parallelism as its theme. There were four speakers who presented various angles on how to parallelize SystemC models. The presentations and following discussion provided a variety of perspectives on threading as it can be applied in virtual platforms and other computer architecture simulations. It was pretty clear that the presenters and audience had quite different ideas about just what the target domain looks like and the best way to introduce parallelism to SystemC. Here is my take on what was said.

Some Notes on Temporal Decoupling (Reposted)

This blog post was originally posted at Intel back in 2018, but it has since been retired from the Intel blog system. As it is of general interest (in my opinion), here is a reposting (with a few small updates here and there).

Temporal decoupling is a key technology in virtual platforms, and can speed up the execution of a system by several orders of magnitude. In my own experiments, I have seen it provide a speedup of more than 1000x. Here, I will dig a little deeper into temporal decoupling and its semantic effects.

Don’t Look behind the Curtain! (Please)

In a previous blog, I talked a bit about the hazards of coding to an implementation and not a specification, based on 1980s home computers. While the specifics and peculiarities of that case is hopefully confined to old hardware, the lessons are still worth contemplating. There is a modern variant of this phenomenon that is based on open-source software, and that I must admit to feeling a bit annoyed by. Fundamentally, the question is this: when figuring out how to use an API – should you look at the documentation or the implementation?