The 2022 DVCon (Design and Verification) Europe conference was back in physical form at its usual venue at the Holiday Inn München. It was a great conference, and just like at the 2022 DAC people were very happy to be back in person.Continue reading “DVCon Europe 2022. Verification, System Simulation, and People!”
DVCon (Design and Verification Conference) Europe is coming up in early December, in person, in München, Germany. The selection of papers and posters is finished, and the program is firming up. I am happy to report that I am part of two items on the menu, a personal record for DVCon! For more on DVCon Europe in general and how it has been in the past, see my previous blog post on DVCon Europe 2022.Continue reading “Two Presentations at DVCON Europe 2022”
The 59th Design Automation Conference (DAC) took place in San Francisco, July 10-14, 2022. As always, the DAC provided a great place to learn about what is going on in EDA. The DAC is really three events in one: there is an industry trade-show/exhibition, a research conference that is considered the premier in EDA, and an engineering track where practitioners present their work in a less formal setting.
I had two talks in the engineering track – one on the Intel device modeling language (which actually won the best presentation award in the embedded sub-track), and one on using simulation technology to build hardware software-first.
The DAC was almost overwhelming in the richness of people and companies, but this blog tries to summarize the most prominent observations.Continue reading “DAC 2022 – Back in Person, Chiplets, an Award, and Much More”
The SystemC Evolution Fika on April 7 had threading/parallelism as its theme. There were four speakers who presented various angles on how to parallelize SystemC models. The presentations and following discussion provided a variety of perspectives on threading as it can be applied in virtual platforms and other computer architecture simulations. It was pretty clear that the presenters and audience had quite different ideas about just what the target domain looks like and the best way to introduce parallelism to SystemC. Here is my take on what was said.Continue reading “SystemC Evolution Fika: Parallel SystemC”
The Design and Verification Conference (DVCon) Europe is going to be in-person in München again in 2022. After two years of virtual conferences, we are going back to the Holiday Inn where we have had so many great events in the past. The conference takes place on December 6 and 7. The call for papers, tutorials, and panels is out now, with a deadline in May!Continue reading “DVCon Europe 2022 – Come Join us in München in December”
When discussing the design and integration of systems on chip and models of systems on chip, the Lego analogy is often brought up. The idea being that with Lego, anyone can put together anything and every component can be combined with all other components. Right. My recent building of Lego set 21327, Typewriter, makes me wonder if the people who talk about Lego-like construction have actually built anything from Legos in the past few decades.Continue reading “Easy to Assemble, just like Lego – Right…”
Just like in 2020, the Design and Verification Conference (DVCon) Europe 2021 was a virtual conference. It took place from October 26 to 27, with the SystemC Evolution day on October 28 (as usual). As has been the case in recent years, the verification side of the conference is significantly larger than the design side. This is common with the other DVCon conferences in the world. In this blog, I will go through my main observations from DVCon Europe, and share some notes from some of the presentations.Continue reading “DVCon Europe 2021 – Testbenches, AI, and Open Source”
DVCon Europe is coming up in late October. This year, I am going to present a tutorial on using the public release of the Intel Simics Simulator to model a PCIe-attached accelerator subsystem. It is fun to be back speaking at the DVCon, after a couple of years of not having talked at the conference. DVCon Europe is a virtual event this year too due to Covid.Continue reading “Presenting a Simics Tutorial at DVCon Europe (2021)”
The Design and Verification Conference Europe (DVCon Europe) took place back in late October 2020. In a normal year, we would add “in München, Germany” to the end of that sentence. But that is not how things were done in 2020. Instead, it was a virtual conference with world-wide attendance. Here are my notes on what I found the most interesting from the conference (for various reasons, this text did come out with a bit of delay).Continue reading “DVCon Europe 2020 – Developing Hardware like Software?”
I have attended the Design Automation Conference (DAC) occasionally for the past decade – maybe every second or third year. The DAC is typically mostly about the lower levels and the backend of hardware design, but there is always something to learn about virtual platforms and related topics closer to my interests. This year, like last year, I got a presentation (and poster) accepted for the Designer track. The DAC organizers held out hope for a physical conference for quite a while (back in early March it seemed rather unlikely that this would still be with us in July…). However, a physical conference was not to be, and the DAC switched to a virtual format in early May.Continue reading “The Virtual DAC 2020”
Last week was spent at the Design Automation Conference (DAC) in Las Vegas. I had a presentation and poster in the Designer/IP track about Clouds, Containers, and Virtual Platforms , and worked in the Intel Simulation Solutions booth at the show floor. The DAC was good as always, meeting many old friends in the industry as well as checking out the latest trends in EDA (hint: same trends as everywhere else). One particularly nice surprise was a book (the printed type, not the Vegas “book” that means something else entirely).Continue reading “DAC 2019 – Cloud, a Book, an Award, and More”
The Embedded World Exhibition and Conference 2019 is coming up in the last week of February. I will be there presenting a paper in the conference as well as demoing CoFluent in the Intel booth and some other miscellany. The paper “Shifting-Left Together – Enabling the Ecosystem with Virtual Platforms” is about how silicon vendors can (should) use virtual platforms to bring shift-left practices to their customers in addition to their own internal teams.Continue reading “Shifting Left Together at the Embedded World 2019”
inThere will be a session on checkpointing in SystemC at the upcoming SystemC Evolution Day in München on October 18, 2017. I will be presenting it, together with some colleagues from Intel. Checkpointing is a very interesting topic in its own right, and I have written lots about it in the past – both as a technology and it applications.
I have posted a two-part blog post to the public Intel Developer Zone blog, about the “Small Batches Principle” and how simulation helps us achieve it for complicated hardware-software systems. I found the idea of the “small batch” a very good way to frame my thinking about what it is that simulation really brings to system development. The key idea I want to get at is this:
[…] the small batches principle: it is better to do work in small batches than big leaps. Small batches permit us to deliver results faster, with higher quality and less stress.
The September 2013 issue of the Intel Technology Journal (which actually arrived in December) is all about Simics. Daniel Aarno of Intel and I served as the content architects for the issue, which meant that we managed to contributed articles from various sources, and wrote an introductory article about Simics and its usage in general. It has taken a while to get this journal issue out, and now that it is done it feels just great! I am very happy about the quality of all the ten contributed articles, and reading the final versions of them actually taught me some new things you could do with Simics! I already wrote about the issue in a Wind River blog post, so in this my personal blog I want to be a little bit more, well, personal.