Computer simulation, programming, software, technology, research, and more (since 2007)
I have now posted my first blog post in the Cadence Community. It was just a matter of time after the VLAB team got acquired by Cadence earlier in 2025 I guess. The topic is the SDV Europe conference that happened in the first few days of December 2025.
Continue reading “First Cadence Blog Post – SDV Europe”
DVCon Europe 2025 took place on October 14 and 15, with the SystemC Evolution Day on the 16th. I was there, running around talking to people, taking photos, and listening to presentations. Just like it usually is. Great conference, great fun, great learning! The conference dinner was back by popular demand, and there was a lot of virtual platforms.
Continue reading “DVCon Europe 2025 – Virtual Platforms and a Real Party”
After a rather long break, we finally had another Computer and System Architecture Unraveled meetup. This time, we had two speakers talking about virtual platforms. Fredrik Larsson from the Simics team at Intel addressed pre-silicon use cases, and Jakob Engblom from the VLAB Works team at Cadence (i.e., myself) talked about uses in Automotive and embedded (mostly post-silicon).
Continue reading ““Pre-Silicon and Post-Silicon Virtual Platforms” – Computer and System Architecture Unraveled Event Six”
The 62nd Design Automation Conference (DAC 62) took place in San Francisco, California, USA, from June 22 to 25, 2025. It was the first time in three years that I attended the DAC (this blog is a little bit late, sorry for that). For those that do not know, the DAC is the biggest show in EDA, combining a major research conference with an industry exhibition and engineering track. This year the theme was AI (Artificial Intelligence), and not much else.
Continue reading “DAC 2025 – All About AI”
In late May, the VLAB Works part of ASTC was acquired by Cadence, and as a result I am finally working in EDA for real. What a change! When I started working with the Simics simulator at Virtutech in 2002, we were at pains to distance ourselves from EDA. Now, almost 25 years later, I am working in one of the big three EDA companies.
Continue reading “Working in EDA for Real (Finally)”
The 2023 DVCon (Design and Verification) Europe conference took place on November 14 and 15, in the traditional location of the Holiday Inn Munich City Center. This was the 10th time the conference took place, serving as an excuse for a great anniversary dinner. Also new was the addition of a research track to provide academics publishing at the conference with the academic credit their work deserves. This year had a large number of papers related to virtual platforms, so writing this report has taken me longer than usual. There was just so much to cover.
Continue reading “DVCon Europe 2023 – 10th Anniversary Edition”
The 59th Design Automation Conference (DAC) took place in San Francisco, July 10-14, 2022. As always, the DAC provided a great place to learn about what is going on in EDA. The DAC is really three events in one: there is an industry trade-show/exhibition, a research conference that is considered the premier in EDA, and an engineering track where practitioners present their work in a less formal setting.
I had two talks in the engineering track – one on the Intel device modeling language (which actually won the best presentation award in the embedded sub-track), and one on using simulation technology to build hardware software-first.
The DAC was almost overwhelming in the richness of people and companies, but this blog tries to summarize the most prominent observations.
Continue reading “DAC 2022 – Back in Person, Chiplets, an Award, and Much More”
Last week was spent at the Design Automation Conference (DAC) in Las Vegas. I had a presentation and poster in the Designer/IP track about Clouds, Containers, and Virtual Platforms , and worked in the Intel Simulation Solutions booth at the show floor. The DAC was good as always, meeting many old friends in the industry as well as checking out the latest trends in EDA (hint: same trends as everywhere else). One particularly nice surprise was a book (the printed type, not the Vegas “book” that means something else entirely).
Continue reading “DAC 2019 – Cloud, a Book, an Award, and More”
The 46th Design Automation Conference (DAC) is coming up in San Francisco in the US, last week of July. For me, this will be the first time I ever go to DAC. I have been to a couple of Design Automation and Test Europe (DATE) conferences before, but DAC is supposedly even bigger as an event for the EDA and related communities. I have the honor to be on a panel this year, as well as co-authoring a paper on software validation.
I while ago I wrote a blog post on checkpointing in virtual platforms, and what it is good for. Checkpointing has been a fairly rare feature in virtual platform tools for some reason, but it seems to be picking up some implementations. In particular, I recently noticed that Cadence added it to their simulator solutions a while ago (2007 according to their blog posts). There are a two blog posts by George Frazier of Cadence (“saving boot time” and “advanced usage“) that offer some insight into what is going on.
Another Cadence guest blog entry, about the overall impact of virtual platforms on the interaction between hardware and software designers. Essentially, virtual platforms are a great tool to make software and hardware people talk to each other more, since it provides a common basis for understanding.
Continue reading “Cadence Industry Insight: “Virtual Platforms Unite HW and SW””
Virtutech and Cadence yesterday announced the integration of Virtutech Simics and Cadence ISX (Incisive Software Extensions), which is essentially a directed random test framework for software. With this tool integration, you can systematically test low-level software and the hardware-software (device driver) interface of a system, leveraging a virtual platform.
Continue reading “Guest Blog at Cadence: “Way Worse than the Real Thing””
Over the past few weeks there was a interesting exchange of blog posts, opinions, and ideas between Frank Schirrmeister of Synopsys and Ran Avinun of Cadence. It is about virtual platforms vs hardware emulation, and how to do low-power design “properly”. Quite an interesting exchange, and I think that Frank is a bit more right in his thinking about virtual platforms and how to use them. Read on for some comments on the exchange.
Continue reading “Cadence-Ran vs Synopsys-Frank over Low-Power and Virtual Things”
Cadence technical blogger Jason Andrews wrote a short piece a couple of days ago on his perception that host-based execution is becoming unncessary thanks to fast virtual platforms. In “Is Host-Code Execution History“, he tells the story of a technique from long time ago where a target program was executed directly on the host, and memory accesses captured and passed to a Verilog simulator. The problem being solved was the lack of a simulator for the MIPS processor in use, and the solution was pretty fast and easy to use. Quite interesting, and well worth a read.
However, like all host-compiled execution (which I also like to call API-level simulation) it suffered from some problems, and virtual platforms today might offer the speed of host-compiled simulation without all the problems.
Continue reading “Cadence on Virtual Prototypes instead of Host Execution”
In early July, Cadence announced their new “C2S” C-to-silicon compiler. This event was marked with some excitement and blogging in the EDA space (SCDSource, EDN-Wilson, CDM-Martin, to give some links for more reading). At core, I agree that what they are doing is fairly cool — taking an essentially hardware-unrelated sequential program in C and creating hardware from it. The kind of heavy technology that I have come to admire in the EDA space.
But I have to ask: why start with C?