DVCon Europe 2022. Verification, System Simulation, and People!

The 2022 DVCon (Design and Verification) Europe conference was back in physical form at its usual venue at the Holiday Inn München. It was a great conference, and just like at the 2022 DAC people were very happy to be back in person.

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Notes from our DVCon Europe 2022 Tutorial

I presented a tutorial about the “verification of virtual platforms models” at DVCon Europe last week. The tutorial was prepared by me and Ola Dahl at Ericsson, but Ola unfortunately could not attend and present his part – so I had to learn his slides and style and do my best to be an Ola stand-in (tall order, we really missed you there Ola!). The title maybe did not entirely describe the contents – it was more a discussion around how to think about correctness and in particular specifications vs implementations. The best part was the animated discussion that we got going in the room, including some new insights from the audience that really added to the presented content.

Updated: Included an important point on software correctness that I forgot in the first publication.

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Two Presentations at DVCON Europe 2022

DVCon (Design and Verification Conference) Europe is coming up in early December, in person, in München, Germany. The selection of papers and posters is finished, and the program is firming up. I am happy to report that I am part of two items on the menu, a personal record for DVCon! For more on DVCon Europe in general and how it has been in the past, see my previous blog post on DVCon Europe 2022.   

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DVCon Europe 2022 – Come Join us in München in December

The Design and Verification Conference (DVCon) Europe is going to be in-person in München again in 2022. After two years of virtual conferences, we are going back to the Holiday Inn where we have had so many great events in the past. The conference takes place on December 6 and 7. The call for papers, tutorials, and panels is out now, with a deadline in May!

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Blog – Damn the Torpedoes, Full Code Ahead!

I have recently got back to developing training labs for the Simics simulator (and related technologies).  During the process of developing a new accelerator model using as many of the latest frameworks and APIs as possible, it was basically guaranteed that I would hit some bugs and unexpected behaviors. That is a natural part of and benefit from creating training materials in the first place. It also provides a good illustration of two fundamentally different ways to look at software development. One is to play it safe and get things done in known ways, and the other is charge ahead, try the unknown, and see what happens. Damn the torpedoes, bugs are a benefit. No bug reports, no glory. In this post, I will share some recent examples of just coding ahead and breaking thing.

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DVCon Europe 2021 – Testbenches, AI, and Open Source

Just like in 2020, the Design and Verification Conference (DVCon) Europe 2021 was a virtual conference. It took place from October 26 to 27, with the SystemC Evolution day on October 28 (as usual). As has been the case in recent years, the verification side of the conference is significantly larger than the design side. This is common with the other DVCon conferences in the world. In this blog, I will go through my main observations from DVCon Europe, and share some notes from some of the presentations.

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Presenting a Simics Tutorial at DVCon Europe (2021)

DVCon Europe is coming up in late October. This year, I am going to present a tutorial on using the public release of the Intel Simics Simulator to model a PCIe-attached accelerator subsystem. It is fun to be back speaking at the DVCon, after a couple of years of not having talked at the conference. DVCon Europe is a virtual event this year too due to Covid.

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About Virtual Events

Just like most people who can, I have been working from home since March 2020 due to Covid-19. Now that we are hopefully seeing the end of the pandemic in the west, it is worth looking back at the conference-from-home aspect of work-from-home. I have seen our Simics training, the Design Automation Conference (DAC), the Design and Verification Conference (DVCon) Europe, commercial training events, talks at industry conferences, guest lectures, and multiple internal Intel events go virtual.  It has been interesting to see how this has worked out, and it seems to me that we are starting to see some good recurring patterns. People have adapted and figured out how to use video meeting technology better and better.

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DVCon Europe 2020 – Developing Hardware like Software?

The Design and Verification Conference Europe (DVCon Europe) took place back in late October 2020. In a normal year, we would add “in München, Germany” to the end of that sentence. But that is not how things were done in 2020. Instead, it was a virtual conference with world-wide attendance. Here are my notes on what I found the most interesting from the conference (for various reasons, this text did come out with a bit of delay).

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Intel Blog Post: Additional Notes on Temporal Decoupling

A few weeks ago, I talked about temporal decoupling in virtual platforms at DVCon Europe 2018. I just posted some additional notes on the topic temporal decoupling on my Intel blog. In this new blog post, I discuss some more aspects of temporal decoupling, and how it affects simulation semantics. I also explain some of the clever techniques used to minimize the impact of temporal decoupling on the software running on the virtual target system.

Update: The blog post is no longer available on the Intel site, instead it was reposted here on this blog to keep it available on the Internet.

DVCon Europe 2018 / A Few Cool Papers

DVCon Europe took place in München, Bayern, Germany, on October 24 and 25, 2018. Here are some notes from the conference, including both general observations and some details on a few papers that were really quite interesting. This is not intended as an exhaustive replay, just my personal notes on what I found interesting.

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Talking about Temporal Decoupling at DVCon Europe

This year’s Design and Verification Conference and Exhibition (DVCon Europe) takes place on October 24 and 25 (2018).  DVCon Europe has turned into the  best conference for virtual platform topics, and this year is no exception. There are some good talks coming!

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Talking Checkpointing in SystemC at the SystemC Evolution Day 2017

inThere will be a session on checkpointing in SystemC at the upcoming  SystemC Evolution Day in München on October 18, 2017. I will be presenting it, together with some colleagues from Intel. Checkpointing is a very interesting topic in its own right, and I have written lots about it in the past – both as a technology and it applications.

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Presenting about Simics and SystemC at DVCon Europe 2016

I am going to present a paper about our new SystemC Library in Simics, at the DVCon Europe conference taking place in München next month. The paper is titled “Integrating Different Types of Models into a Complete Virtual System – The Simics SystemC* Library”, and I authored it together with my Intel colleagues Andreas Hedström, Xiuliang Wang, and Håkan Zeffer.

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