I tend to get into discussions about computer processor instruction-set architecture (ISA) design. ISA design is far from my day job, but it is an interesting topic where everyone working with computers at the machine level have opinions. Typically based on a mix of personal experience and fond memories of particular machines. This in turn leads to intricate and intriguing arguments. In this blog, I will talk about my take on the current state of instruction sets in industry and the age-old “complexity of instruction set” question.
Continue reading “Useful Instruction Set Computing”Tag: instruction set architecture
“RISC-V in Practice” – Computer and System Architecture Unraveled Event Three
On Wednesday, March 13, we had our third CaSA, Computer and System Architecture Unraveled, meetup. Same place as the previous, the 25th floor of the Kista Science Tower building, thanks to the kind sponsorship of Vasakronan and our collaboration with Kista Science City. The theme this time was “The RISC-V ISA in Practice”, with two speakers named Björn. Another great event!
Continue reading ““RISC-V in Practice” – Computer and System Architecture Unraveled Event Three”Intel Blog: Playing with Instruction Sets in the Public Simics RISC-V Platform
As noted previously, the Public Release of the Intel Simics Simulator has added a simple RISC-V virtual platform.
In my second blog post about the platform, I reconfigure the instruction set, crash Linux, debug the issue, and reconfigure the software to match the hardware.
Does ISA Matter for Performance?
When I grew up with computers, the big RISC vs CISC debate was raging. At the time, in the late 1980s, it did indeed seem that RISC was inherently superior to CISC. SPARCs, MIPS, and Alpha all outpaced boring old x86, VAX and 68000 processors. This turned out to be a historical parenthesis, as the Pentium Pro from Intel showed how RISC-style performance could be mated to a CISC ISA. However, maybe ISAs still do matter.