Intel – Observations from Uppsala

DVCon Europe 2023 – 10th Anniversary Edition

The 2023 DVCon (Design and Verification) Europe conference took place on November 14 and 15, in the traditional location of the Holiday Inn Munich City Center. This was the 10^th time the conference took place, serving as an excuse for a great anniversary dinner. Also new was the addition of a research track to provide academics publishing at the conference with the academic credit their work deserves. This year had a large number of papers related to virtual platforms, so writing this report has taken me longer than usual. There was just so much to cover.

The first Computer and System Architecture Unraveled Event in Kista – Great Speakers, Great Fun!

On the evening of the last Wednesday in September, we had our first CaSA, Computer and System Architecture Unraveled, event. CaSA is a meetup in Kista (Sweden) for people interested in computer architecture, system architecture, and how software and hardware interact down towards the lower levels of the stack. The topic for the inaugural event was “Core Count Explosion: A Challenge for Hardware and Software”, and it was great in some many ways!

The NUC12 Enthusiast

Right when our old NUC5 died, its replacement had been delivered and brought online – a new Intel NUC12 Enthusiast, also known as the NUC12SNKi72 (I work at Intel, but even I find that name a bit obtuse). This is a seriously fast machine in a fairly compact package, even though admittedly not as small as the old NUC5. On the other hand, as a machine with an ambition to be a replacement for a dedicated gaming PC, it sports a dedicated graphics card and not just the integrated graphics typical for the classic NUCs.

This NUC is Dead

Computers can wear out given enough time. I just had an old NUC basically fall apart – on the very day it was being replaced by a new one. The timing is rather too good to be believed, but basically the machine stopped working just when we transitioned to a new NUC. The old one still booted… but running it was questionable due to its many concurrent failure modes.

Two Presentations at DVCON Europe 2022

DVCon (Design and Verification Conference) Europe is coming up in early December, in person, in München, Germany. The selection of papers and posters is finished, and the program is firming up. I am happy to report that I am part of two items on the menu, a personal record for DVCon! For more on DVCon Europe in general and how it has been in the past, see my previous blog post on DVCon Europe 2022.

Intel Blog: Catching a Tricky Bug by Running Simics on Simics

I recently published a long post on the Intel Community Blog, talking about how my colleague Evgeny solved a nicely complicated bug using Simics-on-Simics. The bug involved UEFI, an operating system, SMM, SMI, and virtualization. Just another day in the office (or more like a year, given how long it took to get this one resolved).

DVCon Europe 2020 – Developing Hardware like Software?

The Design and Verification Conference Europe (DVCon Europe) took place back in late October 2020. In a normal year, we would add “in München, Germany” to the end of that sentence. But that is not how things were done in 2020. Instead, it was a virtual conference with world-wide attendance. Here are my notes on what I found the most interesting from the conference (for various reasons, this text did come out with a bit of delay).

Intel Blog Post: Shift-Left for a Snowy Ridge

There is a new blog post on the Intel Developer Zone on how we used Simics virtual platforms for the new Intel® Atom® P5900 series of system-on-chip (previously known as Snow Ridge). It talks about how shift-left works both inside of Intel and with our customers for the new chip, and the kinds of virtual platform models you use for different types of use cases.

See https://software.intel.com/en-us/blogs/2020/03/17/seeing-the-early-snow-on-the-ridge

DAC 2019 – Cloud, a Book, an Award, and More

Last week was spent at the Design Automation Conference (DAC) in Las Vegas. I had a presentation and poster in the Designer/IP track about Clouds, Containers, and Virtual Platforms , and worked in the Intel Simulation Solutions booth at the show floor. The DAC was good as always, meeting many old friends in the industry as well as checking out the latest trends in EDA (hint: same trends as everywhere else). One particularly nice surprise was a book (the printed type, not the Vegas “book” that means something else entirely).

Embedded World 2019

The Embedded World in Nürnberg is still going strong as the best tradeshow for “Embedded” in the world. This year, I spent time doing booth duty and gave a talk in the Conference part of the event. There was an unusual high number of old friends and business acquaintances around, and it was a great experience overall with many fruitful discussions and connections for the future. However, it seems that there is always something that goes slightly awry with my travel to the show…

Talking about Temporal Decoupling at DVCon Europe

This year’s Design and Verification Conference and Exhibition (DVCon Europe) takes place on October 24 and 25 (2018). DVCon Europe has turned into the best conference for virtual platform topics, and this year is no exception. There are some good talks coming!

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Intel Blog Post: Looking at the Instruction Mix of Windows 10

In a previous Intel blog post “Question: Does Software Actually Use New Instruction Sets?” I looked at the kinds of instructions used by few different Linux setups, and how each setup was affected by changing the type of the processor it was running on (comparing Nehalem to Skylake). As a follow-up to that post, I have now done the same for Microsoft* Windows* 10. In the blog post, I take a look at how Windows 10 behaves across processor generations, and how its behavior compares to Ubuntu* 16 (they are actually pretty similar in philosophy).

Intel Blog: Question: Does Software Actually Use New Instruction Sets?

Over time, Intel and other processor core designers add more and more instructions to the cores in our machines. A good question is how quickly and easily new instructions added to an Instruction-Set Architecture (ISA) actually gets employed by software to improve performance and add new capabilities. Considering that our operating systems and programs are generally backwards-compatible, and run on all kind of hardware, can they actually take advantage of new instructions?

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”Figure out What to Do”, Says the Manual

I just spend some hours building a new living room PC for the home. I based on common components like a Fractal Design Node 202 chassis and an MSI Z270i motherboard for my Intel Core i7-7700 processor. Trying to figure out how to put it together was a bit interesting though – especially if I had tried to do so without the help of the Internet. The manuals that came with some of the components were just completely useless, essentially boiling down to “please figure out what to do”.

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Clocks or Cores? Choose One

Once upon a time, when multicore processors were novelties, multicore was motivated by the simple fact that it was impossible to keep raising the clock frequency of processors. More “clocks” simply would result in an overheated mess. Instead, by adding more cores, much more performance could be obtained without having to go to extreme frequencies and power budgets. The first multicore processors pretty much kept clock frequencies of the single-core processors preceding them, and that has remained the mainstream fact until today. Desktop and laptop processors tend to stay at 4 cores or less. But when you go beyond 4 cores, clock frequencies tend to start to go down in order to keep power consumption per package under control. A nice example of this can be found in Intel’s Xeon lineup.
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