
There are many ways to use threading and parallelization to improve the performance of virtual platforms. It is not always easy to successfully use parallelization – it very much depends on the nature of the workloads and model setup – but when it works it can really help. I recently published a long blog post at Intel, detailing an idealized example of threading for a device model that is shipping in the Simics training package.
Continue reading “Intel Blog: Parallelizing a Virtual Platform Model”
In early July, Cadence announced their new “C2S” C-to-silicon compiler. This event was marked with some excitement and blogging in the EDA space (