The 2023 DVCon (Design and Verification) Europe conference took place on November 14 and 15, in the traditional location of the Holiday Inn Munich City Center. This was the 10th time the conference took place, serving as an excuse for a great anniversary dinner. Also new was the addition of a research track to provide academics publishing at the conference with the academic credit their work deserves. This year had a large number of papers related to virtual platforms, so writing this report has taken me longer than usual. There was just so much to cover.Continue reading “DVCon Europe 2023 – 10th Anniversary Edition”
I recently added a blog post to the Intel Software blog about how the Intel Simics Simulator executes target-software instructions. The blog post appeared just before DVCon Europe (last week) and I did not have time to put a reflector here earlier.Continue reading “Intel Blog: How Simics Executes Instructions”
In my third post based on the Simics RISC-V simple virtual platform, I use the it to demonstrate how the Intel Simics simulator uses multiple host threads to simulate multiple target cores. The RISC-V platform is nice in that it has less noise than more complex platforms, allowing for clear and simple measurements.
While working on some screenshots for an upcoming blog, I noticed something that something was off with the performance of Simics on my Windows 11 laptop. The CPU load did not quite go as high as I am used to – typically, compute-intense run should get close to 100% processor load using a single host thread to execute the simulation. Instead, I got to no more than about 50%, which was decidedly odd. I also had a screenshot from a few days earlier that showed some 90% CPU load. Turns out the culprit was a combination of factors, including the Windows 11 scheduler and the Corsair iCUE software pack.Continue reading “That’s Odd: How iCue and Windows 11 Ruin Simics Performance”
The 2023-19 version of the Public Release of the Intel Simics Simulator added a simple RISC-V virtual platform. This is the second architecture supported by the public release, after x86.
I will be producing a series of blog posts to show a bit of what the you can do with this virtual platform. The first Intel blog post talks about system-level simulation use cases, in particular networking and simulating x86 and RISC-V systems together.
Update: The article is now available online in HTML format.
I recently published a long post on the Intel Community Blog, talking about how my colleague Evgeny solved a nicely complicated bug using Simics-on-Simics. The bug involved UEFI, an operating system, SMM, SMI, and virtualization. Just another day in the office (or more like a year, given how long it took to get this one resolved).
Today I observed something very odd in Powerpoint. I was pasting in some text from the Simics command-line interface into a text box in Powerpoint to show the output of some commands. Commands whose output relied on box-drawing characters to produce nice tables. But for some reason… it did not work in Powerpoint. Weird.Continue reading “Was this a UTF-8 WTF?”
The SystemC Evolution Fika on April 7 had threading/parallelism as its theme. There were four speakers who presented various angles on how to parallelize SystemC models. The presentations and following discussion provided a variety of perspectives on threading as it can be applied in virtual platforms and other computer architecture simulations. It was pretty clear that the presenters and audience had quite different ideas about just what the target domain looks like and the best way to introduce parallelism to SystemC. Here is my take on what was said.Continue reading “SystemC Evolution Fika: Parallel SystemC”
This blog post was originally posted at Intel back in 2018, but it has since been retired from the Intel blog system. As it is of general interest (in my opinion), here is a reposting (with a few small updates here and there).
Temporal decoupling is a key technology in virtual platforms, and can speed up the execution of a system by several orders of magnitude. In my own experiments, I have seen it provide a speedup of more than 1000x. Here, I will dig a little deeper into temporal decoupling and its semantic effects.Continue reading “Some Notes on Temporal Decoupling (Reposted)”
I have recently got back to developing training labs for the Simics simulator (and related technologies). During the process of developing a new accelerator model using as many of the latest frameworks and APIs as possible, it was basically guaranteed that I would hit some bugs and unexpected behaviors. That is a natural part of and benefit from creating training materials in the first place. It also provides a good illustration of two fundamentally different ways to look at software development. One is to play it safe and get things done in known ways, and the other is charge ahead, try the unknown, and see what happens. Damn the torpedoes, bugs are a benefit. No bug reports, no glory. In this post, I will share some recent examples of just coding ahead and breaking thing.Continue reading “Blog – Damn the Torpedoes, Full Code Ahead!”
DVCon Europe is coming up in late October. This year, I am going to present a tutorial on using the public release of the Intel Simics Simulator to model a PCIe-attached accelerator subsystem. It is fun to be back speaking at the DVCon, after a couple of years of not having talked at the conference. DVCon Europe is a virtual event this year too due to Covid.Continue reading “Presenting a Simics Tutorial at DVCon Europe (2021)”
I have a post out on the Intel Software blog about my experience developing and delivering training for Simics over the past few years. A key observation is that building training is a great way to test the product, and drives changes and improvements in the product. The blog is found at https://software.intel.com/content/www/us/en/develop/articles/teaching-users-drives-product-improvements-in-simics-sw.htmlContinue reading “Intel Blog: How Teaching Users Drives Product Improvements in Simics”