Computer simulation, programming, software, technology, research, and more (since 2007)
The past few days here at DAC, a big theme has been transaction level modeling (TLM).
TLM is often considered to be SystemC TLM-2.0. Most of the statements from the EDA companies are to the effect that SystemC TLM-2.0 solves the problem of combining models from different sources. Scratching the surface of this happy picture, it is clear that it is not that simple…
Virtutech and Cadence yesterday announced the integration of Virtutech Simics and Cadence ISX (Incisive Software Extensions), which is essentially a directed random test framework for software. With this tool integration, you can systematically test low-level software and the hardware-software (device driver) interface of a system, leveraging a virtual platform.
Continue reading “Guest Blog at Cadence: “Way Worse than the Real Thing””
Back in 2001, while a PhD student at Uppsala University and IAR Systems, I wrote what has to be the most popular and long-lived article I ever did: “Getting the Least out of Your C Compiler“. It was an Embedded Systems Conference class that I also presented in 2002 (after that, I changed jobs to Virtutech and therefore C programming was no longer my official topic). However, the text has lived on. It was featured as a chapter in the “Firmware Handbook” edited by Jack Ganssle, translated into German by IAR Germany, and has popped up in various places from time to time.
Last week, it resurfaced at Embedded.com, with an attribution that was initially wrong.
Continue reading “Getting the Least of our your C Compiler – The Best Article I have ever written?”