Seems like the next step after that has a processor called “z6″, and the slide below, taken from a nice presentation available on-line from IBM, appears to indicate that the actual machines will also be called “z6″. Wikipedia has a different opinion, stating that the next-gen mainframes will appear on 2008 Feb 26, and be called z10. Update: the machines are called z10, while the CPU is called z6. Quite logical. But I leave my mis-speculation in here for the record anyway.
Interestingly, that is just two days from now, so we will soon find out. I am posting this post anyway now, since the name is the least interesting
The new processor powering it has some interesting properties, including on-chip accelerators for various functions.
First of all, it seems to be a quite close relative to the Power6 processor. It also aims for very high clocks and the CPU architecture (slide 7) also mentions grouping of instruction and other ideas that are similar to the Power4/5/6 lineage of chips. The “z6″/”power6″ common number “6″ is likely an accident, since IBM has been counting up to that level with the CMOS integrated mainframe processors independently of the Power Architecture development.
The z6 has four cores on a single die rather than the two cores by two threads employed in the Power 5/6. Probably, the different types of applications and ISAs targeted makes threading less
What is the most interesting though is the return of the co-processor, or as they are called nowadays, accelerators. This beast has a decimal floating point unit shared with the Power6 design (one unit inside each core). Similar to Sun’s Niagara 2, there is also compression and cryptography acceleration on the processor chip (one unit shared by two cores). It is not the kind of massive acceleration employed in recent embedded processors, but it is (yet) another sign that heterogeneous computing is becoming fashionable.
From a historical perspective, dedicated accelerators for various specific functions in order to offload the main processors was one of the initial reasons that mainframes could handle the high loads that they did. The “channel controllers” that designed in even back in the 1960s have always been key to the fantastic scaling and robustness of the mainframes. Had they been introduced today, they would have been called “IO accelerators” or “IO offload engines”. In principle, the IBM channel controllers are the grandfathers of today’s TCP/IP accelerators, smart Ethernet controllers, Fibre Channel controllers, and their ilk. So having on-chip acceleration for certain functions that can benefit from high bandwidth memory access and a short communication path to the processor is a very natural evolution for the mainframe architects.