I just had two articles published the Embedded Design part of the EETimes.
First, “Rethink your project planning with a virtual platform“, which talks about how virtual platforms can change your entire project planning. Essentially, by reducing project friction and risks related to hardware availability, software integration, and show-stopper bugs, you can make projects work much better.
Then we have “Transporting bugs with virtual checkpoints“, which is a shorter, popular science, version of the paper I published last year at S4D. This describes how you can use checkpointing in a virtual platform to communicate bugs across time, space, and teams.
The EETimes article Multicore CPUs face slow road in comms piqued my interest. There is an interesting chart in there about just how slow more-than-one-core processors will be in penetrating a vaguely defined “comms” market place. I can believe that, but I think their comments on the PowerQUICC series require some commentary…
Continue reading “EETimes.com – Multicore CPUs face slow road in comms”
I have another short technical piece published about Multicore Debug at the EETimes (and their network of related publications, like Embedded.com). Pretty short piece, and they cut out some bits to make it fit their format. Nothing new to fans of virtual platforms for software development, basically we can use virtual platforms to reintroduce control over parallel and for all practical purposes chaotic hardware/software systems.
As a follow-up to my previous post on the scope of ESL, I found a nice tidbit in an EETimes article… basically saying that hardware design is declining inside the typical system houses.
Continue reading “System Companies leaving the ASIC Business”
Spotted at EETimes.com – Odd move: AMD plans three-core CPU . Interesting that someone in the mainstream finally breaks the 1-2-4-8 progression that seems to be the norm.
Continue reading “AMD three-core Phenom”