DVCon (Design and Verification Conference) Europe is coming up in early December, in person, in München, Germany. The selection of papers and posters is finished, and the program is firming up. I am happy to report that I am part of two items on the menu, a personal record for DVCon! For more on DVCon Europe in general and how it has been in the past, see my previous blog post on DVCon Europe 2022.Continue reading “Two Presentations at DVCON Europe 2022”
The Mathworks Automotive Conference (MAC) 2022 was one-day vendor-specific conference about how Mathworks products can be/are used in the automotive sector. The set of companies represented was truly impressive. There were presentations from Lightyear, MAN, Mercedes-Benz, Volvo, Infineon, Toyota, Bosch, Continental, Real-Time Innovations, and of course the Mathworks themselves. It was a day well-spent listening to interesting talks. Here is my personal summary.Continue reading “The Mathworks Automotive Conference (MAC) 2022”
The 59th Design Automation Conference (DAC) took place in San Francisco, July 10-14, 2022. As always, the DAC provided a great place to learn about what is going on in EDA. The DAC is really three events in one: there is an industry trade-show/exhibition, a research conference that is considered the premier in EDA, and an engineering track where practitioners present their work in a less formal setting.
I had two talks in the engineering track – one on the Intel device modeling language (which actually won the best presentation award in the embedded sub-track), and one on using simulation technology to build hardware software-first.
The DAC was almost overwhelming in the richness of people and companies, but this blog tries to summarize the most prominent observations.Continue reading “DAC 2022 – Back in Person, Chiplets, an Award, and Much More”
I recently published a long post on the Intel Community Blog, talking about how my colleague Evgeny solved a nicely complicated bug using Simics-on-Simics. The bug involved UEFI, an operating system, SMM, SMI, and virtualization. Just another day in the office (or more like a year, given how long it took to get this one resolved).
Back in 2016, the European Space Agency (ESA) lost the Schiaparelli Mars lander during its descent to the surface on Mars. From a software engineering and testing perspective, the story of why the landing failed (see for example the ESA final analysis, Space News, or the BBC) is instructive. It comes down to how software is written and tested to deal with unexpected inputs in unexpected circumstances. I published a blog post about this right after the event and before the final analysis was available. Thankfully, that has since been retired from its original location-it was a bit too full of speculation that turned out to be incorrect… So here is a mostly rewritten version of the post, quoting the final analysis and with new insights.Continue reading “The ESA Schiaparelli Crash & Simulation”
The SystemC Evolution Fika on April 7 had threading/parallelism as its theme. There were four speakers who presented various angles on how to parallelize SystemC models. The presentations and following discussion provided a variety of perspectives on threading as it can be applied in virtual platforms and other computer architecture simulations. It was pretty clear that the presenters and audience had quite different ideas about just what the target domain looks like and the best way to introduce parallelism to SystemC. Here is my take on what was said.Continue reading “SystemC Evolution Fika: Parallel SystemC”
This blog post was originally posted at Intel back in 2018, but it has since been retired from the Intel blog system. As it is of general interest (in my opinion), here is a reposting (with a few small updates here and there).
Temporal decoupling is a key technology in virtual platforms, and can speed up the execution of a system by several orders of magnitude. In my own experiments, I have seen it provide a speedup of more than 1000x. Here, I will dig a little deeper into temporal decoupling and its semantic effects.Continue reading “Some Notes on Temporal Decoupling (Reposted)”
I have recently got back to developing training labs for the Simics simulator (and related technologies). During the process of developing a new accelerator model using as many of the latest frameworks and APIs as possible, it was basically guaranteed that I would hit some bugs and unexpected behaviors. That is a natural part of and benefit from creating training materials in the first place. It also provides a good illustration of two fundamentally different ways to look at software development. One is to play it safe and get things done in known ways, and the other is charge ahead, try the unknown, and see what happens. Damn the torpedoes, bugs are a benefit. No bug reports, no glory. In this post, I will share some recent examples of just coding ahead and breaking thing.Continue reading “Blog – Damn the Torpedoes, Full Code Ahead!”
Just like in 2020, the Design and Verification Conference (DVCon) Europe 2021 was a virtual conference. It took place from October 26 to 27, with the SystemC Evolution day on October 28 (as usual). As has been the case in recent years, the verification side of the conference is significantly larger than the design side. This is common with the other DVCon conferences in the world. In this blog, I will go through my main observations from DVCon Europe, and share some notes from some of the presentations.Continue reading “DVCon Europe 2021 – Testbenches, AI, and Open Source”
DVCon Europe is coming up in late October. This year, I am going to present a tutorial on using the public release of the Intel Simics Simulator to model a PCIe-attached accelerator subsystem. It is fun to be back speaking at the DVCon, after a couple of years of not having talked at the conference. DVCon Europe is a virtual event this year too due to Covid.Continue reading “Presenting a Simics Tutorial at DVCon Europe (2021)”
The International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) XXI conference took place a couple of weeks ago. Like all other events in the past 18 months, it was virtual due to Covid-19. For more on the background on the SAMOS conference, see my blog post about SAMOS XIX (from 2019). This year, I presented a tutorial about our public release of the Simics simulator and took the chance to listen to most of the other conference talks.Continue reading “The SAMOS XXI Conference (Virtual)”
DRAMsys is a simulator for modern RAM systems, built by researchers at Fraunhofer IESE and the Technische Universität Kaiserslautern. Over the past few years, I have heard several talks about the tool and also had the luck to talk a bit to the team behind it. It is an interesting piece of simulation technology, in particular for how it manages to build a truly cycle-accurate model on top of the approximately-timed (AT) style defined SystemC TLM-2.0.Continue reading “DRAMsys – Cycle-Accurate Simulation using Transactions”
The Design and Verification Conference Europe (DVCon Europe) took place back in late October 2020. In a normal year, we would add “in München, Germany” to the end of that sentence. But that is not how things were done in 2020. Instead, it was a virtual conference with world-wide attendance. Here are my notes on what I found the most interesting from the conference (for various reasons, this text did come out with a bit of delay).Continue reading “DVCon Europe 2020 – Developing Hardware like Software?”
I have a post out on the Intel Software blog about my experience developing and delivering training for Simics over the past few years. A key observation is that building training is a great way to test the product, and drives changes and improvements in the product. The blog is found at https://software.intel.com/content/www/us/en/develop/articles/teaching-users-drives-product-improvements-in-simics-sw.htmlContinue reading “Intel Blog: How Teaching Users Drives Product Improvements in Simics”
I have attended the Design Automation Conference (DAC) occasionally for the past decade – maybe every second or third year. The DAC is typically mostly about the lower levels and the backend of hardware design, but there is always something to learn about virtual platforms and related topics closer to my interests. This year, like last year, I got a presentation (and poster) accepted for the Designer track. The DAC organizers held out hope for a physical conference for quite a while (back in early March it seemed rather unlikely that this would still be with us in July…). However, a physical conference was not to be, and the DAC switched to a virtual format in early May.Continue reading “The Virtual DAC 2020”
In the current world-wide lockdown due to Covid-19, many things that were done in-person in the past have to become virtual. The Simics® New User Training that we run at Intel and with our customers and partners is no different. In normal times, we run in-person classes around the world, but that is not an option right now. Thus, we shifted to running remote live classes as a substitute for the time being. This blog shares some of my experience from running remote live classes.Continue reading “Adjusting to Work-from-Home: Remote Live Simics Training”
I have written before about the debug advice to “Quit thinking and look.” It means that you should not form conclusions prematurely. Stop and look at what is going on instead of guessing and cooking up theoretical scenarios. Sound advice that I completely failed to follow in the case that I just chronicled on my Intel Blog: https://software.intel.com/en-us/blogs/2020/03/18/quit-thinking-and-look-chasing-simics-performanceContinue reading “Intel Blog Post: “Quit Thinking and Look” – Mea Culpa Chasing a Performance Bug”
There is a new blog post on the Intel Developer Zone on how we used Simics virtual platforms for the new Intel® Atom® P5900 series of system-on-chip (previously known as Snow Ridge). It talks about how shift-left works both inside of Intel and with our customers for the new chip, and the kinds of virtual platform models you use for different types of use cases.
I have been working with computer simulation and computer architecture for more than 20 years, and one thing that has been remarkably stable over time is the simulation slowdown inherent in “cycle accurate” computer simulation. Regardless of who I talked to or what they were modeling, the simulators ran at around 100 thousand times slower than the machine being modeled. It even holds true going back to the 1960s! However, there is a variant of simulation that aims to make useful performance predictions while running around 10x faster (or more) – mechanistic models (in particular, the Sniper simulator).Continue reading “Simulating Computer Architecture with “Mechanistic” Models – No more 100k Slowdown?”
Earlier this year, Arianna Delsante defended her Master’s Thesis in computer science at Uppsala University. Her thesis topic was to speed up cache and branch prediction simulation in Simics, and in the end she got a speed up of about 10x compared to previous implementations in Simics. I explain a bit more about cache simulation in fast functional simulators and what she did in my latest Intel Developer Zone Blog post, “Speeding-Up Cache Simulation in Simics by 10x“.Continue reading “Intel Blog Post: Simulating Caches 10x Faster with Simics”
A new short blog post on my Intel Developer Zone blog talks about the improved threading simulation core we have added in Simics version 6… and about how a colleague of mine climbed to the top of the highest mountain in Europe and showed a flag with our new Simics icon! Read the story at https://software.intel.com/en-us/blogs/2019/09/10/simics-6-at-the-mountain-top.
I have a new blog post out on the Intel Developer Zone, about the Simics 6 device register coverage feature. I use device register coverage to look at how different operating systems use the same hardware. The differences are significant, demonstrating the (rather expected) observation that different software stacks use the same hardware in different ways.Continue reading “Intel Blog: Simics 6 Device Register Coverage”
A while ago, Ars Technica reviewed the Mega Sg, a modern clone of the old Sega Genesis gaming system. I stumbled on this review recently and realized that this is a fascinating piece of hardware. The Mega Sg is produced by a company called Analogue (https://www.analogue.co/), presumably named thus because they create analogues to old gaming consoles. The way this is done is different from most current “revive the old consoles” products that simply use software emulation to run old games. Instead, Analogue seems to have settled on using FPGA (Field-Programmable Gate Array) technology to basically build new hardware that is functionally equivalent to the old console hardware.Continue reading “Using FPGAs to Simulate old Game Consoles”
Earlier in July 2019, I had the honor of presenting one of the keynote talks at the 19th SAMOS (International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation) conference, held on the island of Samos in Greece. When I got the invite, I had no real idea what to expect. I asked around a bit and people said it was a good conference with a rather special vibe. I think that is a very good description of the conference: a special vibe. In addition to the usual papers and sessions, there is a strong focus on community and social events, fostering discussion across academic disciplines and between industry and academia. There were many really great discussions in addition to the paper and keynote presentations, and overall it was one of the most interesting conferences I have been to in recent years.Continue reading “SAMOS 2019 – Insights, Mechanisms, Heterogeneity, and more”
For Simics training and demo purposes, we often use Linux* running on the virtual platforms. In the early days of Simics and embedded Linux, we built our own minimal configurations by hand to run on simple target systems. Most recently, we changed our Linux default demo and training setup to use Clear Linux*. This change showed us just how sophisticated modern Linux setups are – which is good in general, but it also can make some low-level details more complicated.
I wrote an Intel Developer Zone Blog Post about our experience moving to Clear Linux for Simics demos and training, which contains a lot more details of what we observed and did to make this work for our purposes.
Last week was spent at the Design Automation Conference (DAC) in Las Vegas. I had a presentation and poster in the Designer/IP track about Clouds, Containers, and Virtual Platforms , and worked in the Intel Simulation Solutions booth at the show floor. The DAC was good as always, meeting many old friends in the industry as well as checking out the latest trends in EDA (hint: same trends as everywhere else). One particularly nice surprise was a book (the printed type, not the Vegas “book” that means something else entirely).Continue reading “DAC 2019 – Cloud, a Book, an Award, and More”
The US Defense Advanced Projects Agency (DARPA) ran a “Cyber Grand Challenge” in 2016, where automated cyber-attack and cyber-defense systems were pitted against each other to drive progress in autonomous cyber-security. The competition was run on physical computers (obviously), but Simics was used in a parallel flow to check that competitors’ programs were not trying to undermine the infrastructure of the competition rather than compete fairly inside the rules of the competition.Continue reading “Intel Blog Post: Simics in the DARPA Cyber Grand Challenge”
Running Simics inside a container is a topic that has come up several times in recent years. In a two-part Intel Developer Zone blog post, my colleague Mambwe Mumbwa and I discuss both some background on container technology, how and how well Simics can run inside of containers, and what you can with containerized Simicses. Overall, containers offer a very good alternative to virtual machines for running programs like Simics, and the tool ecosystem opens up some exciting new ways to manage Simics installations and simulation instances.
Update: this post was extended to link to both part 1 and part 2 of the blog.Continue reading “Intel Blog Posts: Running Simics in Containers”