In my third post based on the Simics RISC-V simple virtual platform, I use the it to demonstrate how the Intel Simics simulator uses multiple host threads to simulate multiple target cores. The RISC-V platform is nice in that it has less noise than more complex platforms, allowing for clear and simple measurements.
While working on some screenshots for an upcoming blog, I noticed something that something was off with the performance of Simics on my Windows 11 laptop. The CPU load did not quite go as high as I am used to – typically, compute-intense run should get close to 100% processor load using a single host thread to execute the simulation. Instead, I got to no more than about 50%, which was decidedly odd. I also had a screenshot from a few days earlier that showed some 90% CPU load. Turns out the culprit was a combination of factors, including the Windows 11 scheduler and the Corsair iCUE software pack.Continue reading “That’s Odd: How iCue and Windows 11 Ruin Simics Performance”
The 2023-19 version of the Public Release of the Intel Simics Simulator added a simple RISC-V virtual platform. This is the second architecture supported by the public release, after x86.
I will be producing a series of blog posts to show a bit of what the you can do with this virtual platform. The first Intel blog post talks about system-level simulation use cases, in particular networking and simulating x86 and RISC-V systems together.
The 2022 DVCon (Design and Verification) Europe conference was back in physical form at its usual venue at the Holiday Inn München. It was a great conference, and just like at the 2022 DAC people were very happy to be back in person.Continue reading “DVCon Europe 2022. Verification, System Simulation, and People!”
I presented a tutorial about the “verification of virtual platforms models” at DVCon Europe last week. The tutorial was prepared by me and Ola Dahl at Ericsson, but Ola unfortunately could not attend and present his part – so I had to learn his slides and style and do my best to be an Ola stand-in (tall order, we really missed you there Ola!). The title maybe did not entirely describe the contents – it was more a discussion around how to think about correctness and in particular specifications vs implementations. The best part was the animated discussion that we got going in the room, including some new insights from the audience that really added to the presented content.
Updated: Included an important point on software correctness that I forgot in the first publication.Continue reading “Notes from our DVCon Europe 2022 Tutorial”
Update: The article is now available online in HTML format.
DVCon (Design and Verification Conference) Europe is coming up in early December, in person, in München, Germany. The selection of papers and posters is finished, and the program is firming up. I am happy to report that I am part of two items on the menu, a personal record for DVCon! For more on DVCon Europe in general and how it has been in the past, see my previous blog post on DVCon Europe 2022.Continue reading “Two Presentations at DVCON Europe 2022”
The Mathworks Automotive Conference (MAC) 2022 was one-day vendor-specific conference about how Mathworks products can be/are used in the automotive sector. The set of companies represented was truly impressive. There were presentations from Lightyear, MAN, Mercedes-Benz, Volvo, Infineon, Toyota, Bosch, Continental, Real-Time Innovations, and of course the Mathworks themselves. It was a day well-spent listening to interesting talks. Here is my personal summary.Continue reading “The Mathworks Automotive Conference (MAC) 2022”
The 59th Design Automation Conference (DAC) took place in San Francisco, July 10-14, 2022. As always, the DAC provided a great place to learn about what is going on in EDA. The DAC is really three events in one: there is an industry trade-show/exhibition, a research conference that is considered the premier in EDA, and an engineering track where practitioners present their work in a less formal setting.
I had two talks in the engineering track – one on the Intel device modeling language (which actually won the best presentation award in the embedded sub-track), and one on using simulation technology to build hardware software-first.
The DAC was almost overwhelming in the richness of people and companies, but this blog tries to summarize the most prominent observations.Continue reading “DAC 2022 – Back in Person, Chiplets, an Award, and Much More”
I recently published a long post on the Intel Community Blog, talking about how my colleague Evgeny solved a nicely complicated bug using Simics-on-Simics. The bug involved UEFI, an operating system, SMM, SMI, and virtualization. Just another day in the office (or more like a year, given how long it took to get this one resolved).
Back in 2016, the European Space Agency (ESA) lost the Schiaparelli Mars lander during its descent to the surface on Mars. From a software engineering and testing perspective, the story of why the landing failed (see for example the ESA final analysis, Space News, or the BBC) is instructive. It comes down to how software is written and tested to deal with unexpected inputs in unexpected circumstances. I published a blog post about this right after the event and before the final analysis was available. Thankfully, that has since been retired from its original location-it was a bit too full of speculation that turned out to be incorrect… So here is a mostly rewritten version of the post, quoting the final analysis and with new insights.Continue reading “The ESA Schiaparelli Crash & Simulation”
The SystemC Evolution Fika on April 7 had threading/parallelism as its theme. There were four speakers who presented various angles on how to parallelize SystemC models. The presentations and following discussion provided a variety of perspectives on threading as it can be applied in virtual platforms and other computer architecture simulations. It was pretty clear that the presenters and audience had quite different ideas about just what the target domain looks like and the best way to introduce parallelism to SystemC. Here is my take on what was said.Continue reading “SystemC Evolution Fika: Parallel SystemC”
This blog post was originally posted at Intel back in 2018, but it has since been retired from the Intel blog system. As it is of general interest (in my opinion), here is a reposting (with a few small updates here and there).
Temporal decoupling is a key technology in virtual platforms, and can speed up the execution of a system by several orders of magnitude. In my own experiments, I have seen it provide a speedup of more than 1000x. Here, I will dig a little deeper into temporal decoupling and its semantic effects.Continue reading “Some Notes on Temporal Decoupling (Reposted)”